Embodiments relate to a semiconductor device and a method for forming the same, and more particularly to a three-dimensional (3D) n-type metal oxide semiconductor (NMOS) transistor and a three-dimensional (3D) p-type metal oxide semiconductor (PMOS) transistor which are included in a peripheral region.
As the integration degree of a semiconductor device increases, a design rule and a channel length are reduced, such that a buried-channel PMOS transistor requires a high voltage, resulting in deterioration of leakage current characteristics. In order to address the above-mentioned issue, a dual gate structure has been used such that the semiconductor device can be driven at a low voltage.
Meanwhile, in order to provide low cell contact resistance and refresh characteristics in response to reduction of a planar region occupied by electronic components configured to construct the semiconductor device, a three-dimensional structure such as a recess channel gate or a fin-shaped gate has been widely used. If a dual gate scheme comprised of NMOS and PMOS transistors is applied to a three-dimensional cell structure such as a recess channel gate and a fin-shaped gate, high-density doping may be needed.
However, provided that a gate stack is formed to have a higher height because an insulation interval and an active region are reduced in response to reduction of a design rule, it is difficult to define a gate line and gap-fill characteristics are deteriorated.
In addition, since the doping process is carried out by implanting ions into a polysilicon material, a gate stack has a limited height. Since the polysilicon material has a limited thickness of 1000 Å or less, gate depletion and ion penetration may occur, such that there is a need to strictly control ion implantation energy and dose.
Assuming that a PMOS transistor in a peripheral region has a three-dimensional structure such as a recess channel gate, the P+ ion implantation method may not be appropriate to dope a polysilicon material in a high density because boron ions are distributed to an upper tungsten silicide layer or titanium silicide layer when subject to heat. As a result, the polysilicon material has difficulty in maintaining a high density and boron ions permeate into a channel of a silicon substrate, possibly reducing a threshold voltage. Thus, the above-mentioned semiconductor device may have difficulty in forming a 3D dual gate such as a recess channel gate or a fin-type gate in the peripheral region.